In general, a ferroelectric memory is known as one of nonvolatile memories. Such a ferroelectric memory is disclosed in Japanese Patent Laying-Open No. 2001-210795, for example. This conventional ferroelectric memory is a memory utilizing a pseudo-capacitance change responsive to the direction of polarization of a ferroelectric substance as a memory device. The ferroelectric memory is spotlighted as an ideal memory having both of such an advantage that the same can rewrite data at a high speed with a low voltage in principle and such an advantage that the same is nonvolatile.
FIG. 33 is an equivalent circuit diagram showing a memory cell array of an exemplary conventional simple matrix ferroelectric memory. FIG. 34 is a hysteresis diagram for illustrating operations of the exemplary conventional simple matrix ferroelectric memory. Referring to FIG. 33, a memory cell 501 of the exemplary conventional simple matrix ferroelectric memory is constituted of single ferroelectric capacitors 501a consisting of word lines WL and bit lines BL formed to extend in directions intersecting with each other and ferroelectric films (not shown) arranged between the word lines WL and the bit lines BL.
Operations of the exemplary conventional simple matrix ferroelectric memory are now described with reference to FIGS. 33 and 4. Table 1 shows voltages applied to the word lines WL and the bit lines BL in a read operation and a write operation.
TABLE 1StandbyReadWrite“1”Write“0”Selected WL½ VccVcc0VccUnselected WL½ Vcc⅓ Vcc⅔ Vcc⅓ VccSelected BL½ Vcc0→FloatingVcc0Unselected BL½ Vcc⅔ Vcc⅓ Vcc⅔ Vcc
As the write operation, both ends of the ferroelectric capacitors 501a are at the same potentials in a standby state. When writing data “0”, the memory applies a voltage Vcc to a selected word line WL (selected WL) while applying a voltage 0 V to a selected bit line BL (selected BL). At this time, a potential difference Vcc is applied to the ferroelectric capacitors 501a. Thus, the polarization state of the ferroelectric capacitor 501a of a selected memory cell 501 shifts to a point A shown in FIG. 34. When the memory thereafter sets both ends of the ferroelectric capacitor 501a to the same potential, the polarization state of the ferroelectric capacitor 501a makes a transition to “0” shown in FIG. 34. When writing data “1”, the memory applies the voltage 0 V to the selected WL while applying the voltage Vcc to the selected BL. At this time, a potential difference −Vcc is applied to the ferroelectric capacitors 501a (see FIG. 33). Thus, the polarization state of the ferroelectric capacitor 501a of the selected memory cell 501 shifts to a point B in FIG. 34. When the memory thereafter sets both ends of the ferroelectric capacitor 501a to the same potential, the polarization state of the ferroelectric capacitor 501a (see FIG. 33) makes a transition to “1” shown in FIG. 34.
As the read operation, the memory first precharges the selected BL to the voltage 0 V, and thereafter brings the same into a floating state. Then, the memory sets up the selected WL to the voltage Vcc. The current potential difference Vcc between the selected WL and the selected BL is capacitance-divided by CFE and CBL assuming that CFE represents the capacitance of the ferroelectric capacitor 501a (see FIG. 33) and CBL represents the parasitic capacitance of the selected bit line BL. The capacitance CFE of the ferroelectric capacitor 501a can be approximated as C0 or C1 depending on held data (“0” or “1”). Therefore, the potential of the selected bit line BL is expressed by the following expressions (1) and (2):V0={C0/(C0+CBL)}×Vcc  (1)V1={C1/(C1+CBL)}×Vcc  (2)
The above expression (1) indicates the potential V0 of the selected BL when data “0” is held, and the above expression (2) indicates the potential V1 of the selected BL when data “1” is held.
The memory performs data reading by determining the potential difference between the bit line potential V0 of the above expression (1) and the bit line potential V1 of the above expression (2) with a read amplifier. Since data of the memory cell 501 is destroyed in this data reading, the memory performs a rewrite operation (restore) responsive to the read data after the data reading.
In the exemplary conventional simple matrix ferroelectric memory shown in FIG. 33, however, it follows that a potential difference of ⅓ Vcc is applied to all unselected memory cells 501 in the write operation and the read operation, and hence there is such inconvenience that the quantity of polarization of the ferroelectric capacitor 501a decreases due to hysteretic properties of the ferroelectric film, as shown in FIG. 35. Consequently, there is such a problem that such a disturbance phenomenon takes place that data are lost from the unselected memory cells 501.